The total number of bits in semiconductor memory is approaching the gigabit range and beyond. Concurrent with the increase in memory capacity, the dimensions of the circuit components are decreasing. Consequently, the push for more capacity in a smaller space puts pressure on maintaining yield and reducing cost. One approach to improving yield and cost factors involves the use of built-in redundancy cells for replacement of memory arrays. During testing, if a defective cell is found, one of the built-in redundancy cells is configured to replace it. In one well-known process, fuses are used to provide such redundancy in semiconductor memories. If a semiconductor memory is found to have a small number of defective bits, these defects can be effectively overcome by exchanging the cells (as defined by rows and columns) containing the faulty bit locations with spare cells especially designed for this purpose. The address of the row or column that is exchanged and the location of the row or column is programmed into the memory circuitry during test. This is commonly done by opening (i.e., by "blowing" open the fuses) a number of fuses in a special section of the circuit. The fuses can be opened electrically, but it is usually more convenient to open them by subjecting the fuse to a high-intensity focused laser beam on a special probing system.
Any conductive material can be potentially used for the fusible element. For ease of incorporation into an existing integrated circuit, the most commonly used materials are the layer of poly-silicon which is used for the gate electrode, or one of the existing metal interconnect layers. The poly-silicon may be N-type or P-type depending upon the polarity of the transistor structure. A metal layer is usually preferred for the fuse due to its lower inherent resistance, which allows for faster reading of the fuse and faster memory access. The particular composition of the metal depends upon the process used. For example, a "metal" in a modern sub-micron process may be a "sandwich" of layers. The bottom layer has about 200 .ANG. of titanium, a middle layer of 5000 .ANG. of an aluminum/copper alloy and a top layer of about 300 .ANG. of titanium nitride. Depending on the specifics of the process, other types of alloys and configurations may be used.
When the fuse is opened with the laser beam, a great deal of energy is transferred into the fuse, causing a rapid rise in temperature and vaporization of at least part of the fuse. The force of the blast forcibly expels vaporized parts of the fuse. In this way, the fuse changes from a conductive link to a non-conductive link The ease and reproducibility of blowing the fuse in this manner and the reliability of the fuse element once blown are all strongly dependent on the material covering the fuse.
In a conventional integrated circuit, the levels of metal that form the interconnect layers are each embedded in some form of deposited silicon dioxide to guarantee good electrical isolation between the conductors. The upper-most insulating layer, on top of the upper-most metal layer in the integrated circuit, also serves as a "passivation" layer. The passivation layer acts to protect the delicate integrated circuit from both mechanical damage and from the entry of foreign material (such as moisture or ionic contaminants) that might compromise the long-term reliability of the circuit. More commonly, the passivation layer on modern integrated circuits consists of a nitride layer deposited on the oxide layer in the circuit. The nitride layer is used because of its mechanical strength and its impermeability to moisture and ionic contaminants.
An example prior art process fabricates a semiconductor device on a wafer substrate. Upon the wafer substrate, an insulating layer is deposited. Typically, this insulating layer is silicon dioxide. However, other insulators may be used as well. Examples of insulating materials include silicon dioxide, silicon oxynitride, silicon oxyfluoride, silicon nitride, other oxides and nitrides, amorphous carbon, spin-on glasses (e.g., silicates, siloxanes, hydrogen silsesquioxane, and alkyl silsesquioxanes), polymers (e.g., polyimides and fluoropolymers), and other non-conductive materials.
FIG. 1A and FIG. 1B depict an example embodiment of a fuse in cross-section and top-view perspectives, respectively. In FIG. 1A, a device structure 100 has a fuse layer 120 on top of an oxide layer 110. Covering the fuse layer 130 is second oxide layer 130. Upon the second oxide layer 130 is a nitride layer 140.
Photolithography and etching define a fuse layer of a conductive material along with other conductive interconnect (e.g., component-to-component connection within the IC). Such conductive materials may include doped poly-silicon or metal alloys of aluminum, copper, or others. In an example process, the shape of the fuse layer usually has a "dog bone" appearance as shown in FIG. 1B. However, the geometry of the fuse is not limited to any particular form. The form is governed by the needs of the process and application. As is well known, designers are able to design varying valued resistor structures by patterning layers in a variety of different shapes designed to fit well within a particular design layout. By way of example, the resistance "R" of a patterned shape is determined by multiplying the ratio of ("length"/"width") by the resistivity expressed in terms of sheet resistance (i.e., [(L/W).times./]=). The final shape of the fuse determines how much current it may carry, the amount of energy required to open the fuse, and the long-term reliability of the fuse.
Referring to FIG. 1B, a typical implementation of a fuse layer 120 on device structure 100 is shown. Nitride layer 140 is the upper-most layer. For further information on manufacturing and testing of fuses, reference may be made to U.S. Pat. No. 4,455,194 of Yabu et al, "Method for Producing a Semiconductor Device" and U.S. Pat. No. 4,628,590 of Udo et al, "Method of Manufacture of a Semiconductor Device," each incorporated by reference.
For the design of reliable and reproducible fuses, the top passivation layer of the integrated circuit is often a major consideration. For fuse optimization, it is preferable that there not be any nitride film on top of the film. This is because the mechanical robustness of the nitride film tends to resist the vaporization of the fuse material, making it hard to blow the fuse. If sufficient energy is coupled into the fuse to overcome this resistance, the vaporization of the fuse is more explosive, and may tend to damage nearby circuit elements. For this reason, it is usually preferable to remove the nitride layer in the immediate region over the fuse.
Some implementations choose to remove the nitride layer, but leave a layer of silicon dioxide on top of the fuse. One reason is that it improves the integrity of the protective seal on top of the integrated circuit. Because the majority of the fuses in any memory will not be blown, it is desirable that they remain covered with a protective layer of oxide in order to provide a degree of mechanical and chemical protection. A second reason relates to the reliability of fuse blowing. If there is no encapsulating layer on top of the fuse trying to contain the vaporized metal, the fuse can be melted and blown with a relatively small amount of laser energy. If the fuse is blown in this way, the vaporized metal may not be forcibly expelled and may be re-deposited in the vicinity of the remaining fuse body. Over time, this type of structure may tend to become more conductive, and pose a reliability risk to the functionality of the circuit.
In one prior art approach, a circuit is tested while a first passivation film covering a semiconductor substrate, on which circuit elements such as transistors, capacitors and the like are formed, is partially open over the fuses and bonding pads thereof. The fuses are opened, if necessary to wire in the redundant circuit elements. A second passivation film is then formed so as to cover the exposed portions of the fuses and bonding pads. Any cracks in the fuses and bonding pads are thus covered by the second passivation film to prevent their exposure. In this manner, invasion of moisture or the like below the fuses and the bonding pads can be prevented, and moisture proofing as well as the reliability of the semiconductor device can be improved.
The aforementioned process may require that the wafers be removed from the "clean room" environment of the wafer fabrication facility (wafer fab), be tested in a "notso-clean" wafer probe test, and be re-introduced back into the wafer fab for subsequent passivation. These wafers may be re-tested to assure that later process steps do not introduce fatal defects into the devices. Such re-testing reduces the likelihood of packaging failing devices.
In another prior art process of forming a metal fuse and removing the nitride layer, the fuse body is defined in the uppermost level of the metal interconnect on top of a dielectric, usually an oxide, that is available in the integrated circuit. It is then covered by the passivation oxide layer and nitride layer. An additional masking step is performed to open an area immediately on top of the fuse. A special nitride etch is performed to remove the upper nitride layer, but stop on the underlying oxide layer. The resulting structure, after resist removal, is suitable for fuse reliability (a metal fuse covered only with oxide). However, this comes at the expense of adding extra masking and etching steps to the fabrication sequence.
As the number of metal layers used is increased, the building of a suitable fuse covered only with oxide without adding process steps and increasing cost becomes problematic.